• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2022, Volume: 15, Issue: 23, Pages: 1143-1150

Original Article

Analysis of 7T SRAM Cell Based on MTCMOS, SVL and I-SVL Technique

Received Date:25 October 2021, Accepted Date:13 April 2022, Published Date:29 June 2022


Objective: To design and propose an optimized Volatile 7T based SRAM cell in terms of leakage currents and dynamic power. Methods: The methodology involved is Multi threshold Voltage CMOS (MTCMOS), Self Controllable Voltage Level (SVL) and Improved Self Controllable Voltage Level (I-SVL). Findings: The proposed work demonstrates that 7T based SRAM cell using I-SVL method is efficient in terms of leakage currents and dynamic power. Also, Comparative Leakage current and dynamic power analyses are done between MTCMOS, SVL, and I-SVL methods The Proposed work based on I-SVL is significant than the MTCMOS and SVL Technique. All the circuits are developed using the Cadence virtuoso tool and spectre simulator is used to carry out the simulation. Novelty: The paper proposes Low power Volatile Memory cell based on 7T with improvements in leakage and dynamic power values in comparison with the earlier literatures. The proposed I-SVL based cell is 89% and 85% efficient in terms of dynamic power in comparison with the earlier references.

Keywords: Improved – Self Controllable Voltage Level (I-SVL); Improved Lower SVL (I-LSVL); Improved Upper SVL (I-USVL); Multi threshold Voltage CMOS(MTCMOS); Self Controllable Voltage Level (SVL); SRAM


  1. Jyothi K. SRAM cell with MT-SVL Technique for Leakage Power reduction. IT in Industry Journal. 2021;9(2). Available from: https://doi.org/838-1-10-20210413
  2. Shivkumar SA, Geetha S. Design and Analysis of Low power MTCMOS using SRAM Cell. International Journal of Management. 2019;IX(III). Available from: https://doi.org/16.10089.IJMTE.2019.V9I3.19.27426
  3. Nikitha L, Bhargavi NS, Kariyappa BS. Design and Development of Non-volatile Multi-threshold Schmitt Trigger SRAM Cell. International conference on Emerging Research in Electronics. 2019;p. 978–981. Available from: https://doi.org/10.1007/978-981-13-5802-9
  4. Kumar CSH, Kariyappa BS. Analysis of low power 7T SRAM cell employing improved SVL (ISVL) technique. 2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT). 2017;p. 478–482. Available from: https://doi.org/10.1109/ICEECCOT.2017.8284551
  5. Sreekala K, Kumar SK. Leakage Estimation of SRAM cell based on Node Voltage and Current Characterization. International Journal of Pure and Applied Mathematics. 2018;p. 13143395. Available from: https://doi.org/https://acadpubl.eu/jsi/2018-118-7-9/articles/7/13
  6. Kumar H, CS, KB. 7T Based SRAM Topologies with Low Power and Higher SNM. International Journal of Innovative Technology and Exploring Engineering. 2019;8(11):2779–2783. Available from: https://doi.org/10.1109/RTEICT42901.2018.9012414
  7. Tripathi T, Chauhan DS, Singh SK. A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability. Journal of Low Power Electronics and Applications. 2018;8(4):41. Available from: htps://doi.org/ 10.3390/jlpea8040041
  8. RA, Tomar VK. Analysis of Cache (SRAM) Memory for Core iTM 7 Processor, 2018. 9th Int. Conf. Comput. Commun. Netw. Technol. 2018;p. 1–8. Available from: https://doi.org/10.1109/ICCCNT.2018.8494063
  9. Leela M, Rooban S, Joshitha C. Comparative analysis on low power SRAMs. Materials Today: Proceedings. 2020. Available from: https://doi.org/10.1016/j.matpr.2020.11.140
  10. Singh J, Raj B. Design and Investigation of 7T2M-NVSRAM With Enhanced Stability and Temperature Impact on Store/Restore Energy. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2019;27(6):1322–1328. Available from: https://doi.org 10.1109/TVLSI.2019.290103
  11. Kumar CSH, Kariyappa BS. Node Voltage and KCL Model-Based Low Leakage Volatile and Non-Volatile 7T SRAM Cells. IETE Journal of Research. 2022;p. 1–17. doi: 10.1080/03772063.2022.2027279
  12. Chauhan RA. Low Power PPN inverter based 10T SRAM Cell. Indian Journal of Science and Technology. 2021;14(20):1699–1710. Available from: https://doi.org/10.17485/IJST/ v14i20.400
  13. Valluri A, Jayabalan M. Reduction of Power in SRAM cell with Gated Vdd Technology. IJRTE. 2019;7. Available from: https://doi.org/E10800275S419/19@BEIESP


© 2022 Kumar & Kariyappa. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.

Published By Indian Society for Education and Environment (iSee)


Subscribe now for latest articles and news.