Indian Journal of Science and Technology
DOI: 10.17485/ijst/2016/v9i5/87165
Year: 2016, Volume: 9, Issue: 5, Pages: 1-5
Original Article
Sivanantham Sathasivam* and G. Venu Reddy
VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, India; ssivanantham@ vit.ac.in, [email protected]
*Author For Correspondence
Sivanantham Sathasivam VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, India; ssivanantham@ vit.ac.in
Objectives: This paper aims at designing high speed and high throughput Fast Fourier Transform (FFT) processor which is a critical block and is widely used in many Digital Signal Processing applications. Methods: The proposed model works with both real and complex type of input data. Pipelining in the proposed architecture is achieved with single delay feedback methodology. Findings: The CMOS 0.18 µm is used to design Application Specific Integrated Circuit (ASIC) for the proposed FFT processor and it works with an input size of 36 bits at the operating frequency of 100 MHz, occupies an area of 1.27 mm and consumes 39 mW, at an operating voltage of 1.8V.Obtained results are compared with existing methods in terms of input word length, throughput, power dissipation and it shows that the proposed architecture gives high throughput, uses 3x more word length and 2x less power dissipation. Applications: The designed chip can be used in scientific computations since it require less power and operates in high speed.
Keywords: ASIC, Fast Fourier Transform, Pipelining, Single Delay Feedback, Throughput
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