Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 5, Pages: 1-7
S. Ravi* , Subhajit Sinha, R. Adithyan and Harish M. Kittur
VLSI Division, SENSE, VIT University, Vellore - 632014, Tamil Nadu, India; [email protected], [email protected]; [email protected]; [email protected]
*Author For Correspondence
S. Ravi VLSI Division, SENSE, VIT University, Vellore - 632014, Tamil Nadu, India; [email protected]
Background/Objectives: As the complexity of system on chip increases the timing sign-off becomes a challenging task for STA (Static Timing Analysis) engineer. Methods/Statistical Analysis: Due to the wide usage of IP’s, change in power and skew may occur among different regions of chip. To address this issue clock gating and zero skew algorithms are mainly used. It is good design idea to turn off the clock when it is not needed. Findings: This paper proposes a new NOR/OR cells with different driving strengths and a new tunable delay elememt. These designed cells can be used in automatic clock gating which is supported by modern EDA tools. The proposed method of clock buffers with different sizes are designed and compared with ISCAS89 Benchmark circuits (s35932, s38417 and s38584). These components are designed and tested using Cadence ICFB and SOC encounter P&R tool. Applications/Improvements: This clock gating elements can be used in any System-on-a-Chip (SoC) application where minimum skew is required.
Keywords : Clock Gating, Delay Matching, Skew, Tunable Delay, Type Matching
Subscribe now for latest articles and news.