Design and Analysis of Low Power Memory Built in Self Test Architecture for SoC based Design

Sowmithra Vennelakanti   and S  Saravanan

doi:10.17485/ijst/2015/v8i14/62716

Article

Design and Analysis of Low Power Memory Built in Self Test Architecture for SoC based Design

VIEWS 818
PDF 401

Abstract
Full-Text HTML
Full-Text PDF
How to Cite

Indian Journal of Science and Technology

DOI: 10.17485/ijst/2015/v8i14/62716

Year: 2015, Volume: 8, Issue: 14, Pages: 1-5

Original Article

Design and Analysis of Low Power Memory Built in Self Test Architecture for SoC based Design

Sowmithra Vennelakanti^1* and S. Saravanan²

¹VLSI Design, SASTRA University, Thanjavur, India; [email protected]

²School of Computing, SASTRA University, Thanjavur, India; [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

This paper targets on the low power design of Memory Built In Self Test (MBIST) architecture for System on Chip (SoC) based design. Proposed address generator is developed with the blend of gray code counter and modulo counter. Bit reversing technique is adopted in this paper to generate the last pattern of gray code counter. In this work a refined architecture of MBIST is also constructed by embedding a low power address generator in it. Efficient employment of the proposed address generator in MBIST has cut-down the power consumption of BIST architecture compared to the traditional BIST. Reduction of about 6% of switching activity has been observed with novel MBIST architecture.

Keywords: Gray Code, Low-Power, MBIST, Modulo Counter, MUT