• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2023, Volume: 16, Issue: 42, Pages: 3743-3755

Original Article

Design and Analysis of Wideband PNP Sziklai Common Collector Amplifier with High Current Gain

Received Date:21 April 2023, Accepted Date:25 October 2023, Published Date:12 November 2023


Objective: Objective of the manuscript is to introduce a novel idea of designing a small-signal common collector (emitter follower) amplifier with user-defined PSpice model of PNP Sziklai pair. Method: A circuit simulation program is developed on the PSpice simulation platform to design and study the proposed amplifier circuit. Small-signal AC equivalent circuit analysis authenticates the proposed amplifier design and selection of biasing components. The proposed amplifier is also implemented on Cadence Virtuoso Simulation software at 180nm technology to validate the design by performing its layout and post-layout simulation. Findings: The proposed circuit gives high current gain and smaller gain fluctuations (β) due to environmental parameter variations. The effect of variation in stage current gain of Sziklai pair components is observed under different operating conditions. Equivalent circuit analysis, noise performance, and the effect of temperature on the performance of the proposed circuit are widely discussed. Other possible circuit structures with a similar concept of design are also discussed as special cases. Highly stable amplifier current gain as well as device current gain, high amplifier voltage gain, device voltage gains below unity, and low harmonic distortion are prime features of proposed circuit. The problem of finding a matched pair of BJTs for the Sziklai pair is also addressed in the proposed design. The linear distortion-less operation of this circuit, combined with its very high current gain, makes it a suitable candidate for instrumentation amplifiers with wide operating frequency range. The proposed amplifier takes up (10.105 x 10.055) μm2 of area at 180nm technology. The results of pre-layout and post-layout AC responses show that there is a close resemblance between the parameters before and after the layout, which promotes the usability and design of the proposed amplifier. Novelty: The idea explored in the manuscript is entirely new and first time announced by authors.

Keywords: PNP Sziklai Pair, Common Collector Amplifier, Current Gain, Small Signal Amplifier, Cadence Virtuoso


  1. Toledo P, Crovetti PS, Klimach HD, Musolino F, Bampi SM. Low-Voltage, Low-Area, nW-Power CMOS Digital-Based Biosignal Amplifier. IEEE Access. 2022;10:44106–44115. Available from: https://doi.org/10.1109/ACCESS.2022.3168603
  2. Aniles H, Angulo JR, Perez J, Martin A, Carvajal RG. Low-Voltage 0.81mW, 1-32 CMOS VGA With 5% Bandwidth Variations and -38dB DC Rejection. IEEE Access. 2020;8:106310–106321. Available from: https://doi.org/10.1109/ACCESS.2020.2999315
  3. Anisheh SM, Abbasizadeh H, Shamsi H, Dadkhah C, Lee KYY. 98-dB Gain Class-AB OTA With 100 pF Load Capacitor in 180-nm Digital CMOS Process. IEEE Access. 2019;7:17772–17779. Available from: https://doi.org/10.1109/ACCESS.2019.2896089
  4. Shukla SN, Arshad SS, Srivastava G. NPN Sziklai pair small-signal amplifier for high gain low noise submicron voltage recorder. International Journal of Power Electronics and Drive Systems (IJPEDS). 2022;13(1):11. Available from: http://doi.org/10.11591/ijpeds.v13.i1.pp11-22
  5. Shukla SN, Arshad SS, Srivastava G. Novel complementary Sziklai pair based high gain low noise small-signal amplifiers. International Journal of Power Electronics and Drive Systems (IJPEDS). 2023;14(4):2283. Available from: http://doi.org/10.11591/ijpeds.v14.i4.pp2283-2292
  6. Shukla SN, Srivastava G, Arshad SS. Study of Low-Noise Wide-Band Tuned Sziklai Pair Small-Signal Amplifier. Research Trends and Challenges in Physical Science . 2021;1:1–16. Available from: https://doi.org/10.9734/bpi/rtcps/v1/4064F
  7. Arshad SS, Shukla SN, Sharma AK, Srivastava G. Darlington pair based Small-Signal amplifier under triple transistor topology. Journal of International Academy of Physical Sciences. 2022;26(4):427–442. Available from: https://www.iaps.org.in/journal/index.php/journaliaps/article/view/960
  8. Saad P, Hou R. Symmetrical Load Modulated Balanced Power Amplifier With Asymmetrical Output Coupling for Load Modulation Continuum. IEEE Transactions on Microwave Theory and Techniques. 2022;70(4):2315–2327. Available from: https://doi.org/10.1109/TMTT.2022.3147843
  9. Giustolisi G, Palumbo G. Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior. IEEE Transactions on Circuits and Systems I: Regular Papers. 2021;68(3):998–1011. Available from: https://doi.org/10.1109/TCSI.2020.3044454
  10. Li Z, Liu B, Duan Y, Wang Z, Li Z, Zhuang Y. Flat-High-Gain Design and Noise Optimization in SiGe Low-Noise Amplifier for S–K Band Applications. Circuits, Systems, and Signal Processing. 2021;40(6):2720–2740. Available from: https://doi.org/10.1007/s00034-020-01616-2
  11. Hu J, Ma K. Analysis and Design of a Broadband Receiver Front End for 0.1-to-40-GHz Application. IEEE Transactions on Circuits and Systems . 2021;68(6):2393–2403. Available from: https://doi.org/10.1109/TCSI.2021.3064262
  12. Toledo P, Crovetti P, Klimach H, Bampi S, Aiello O, Alioto M. A 300mV-Supply, Sub-nW-Power Digital-Based Operational Transconductance Amplifier. IEEE Transactions on Circuits and Systems II: Express Briefs. 2021;68(9):3073–3077. Available from: https://doi.org/10.1109/TCSII.2021.3084243
  13. Lupo N, Bartolini M, Pulici P, Colli S, Nessi M, Bonizzoni E. On the Linearity of BJT-Based Current-Mode DAC Drivers. IEEE Transactions on Circuits and Systems II: Express Briefs. 2021;68(9):3138–3142. Available from: https://doi.org/10.1109/TCSII.2021.3093657
  14. Kim M, Cho S. A Single BJT Bandgap Reference With Frequency Compensation Exploiting Mirror Pole. IEEE Journal of Solid-State Circuits. 2021;56(10):2902–2912. Available from: https://doi.org/10.1109/JSSC.2021.3093583
  15. Sawigun C, Thanapitak S. A Compact Sub-μW CMOS ECG Amplifier With 57.5-MΩ Z in, 2.02 NEF, 8.16 PEF and 83.24-dB CMRR. IEEE Transactions on Biomedical Circuits and Systems. 2021;15(3):549–558. Available from: https://doi.org/10.1109/TBCAS.2021.3086182
  16. Shukla D, Gupta SK, Bhadauria V, Tripathi RV. High Gain, Low Noise, Low Voltage, and Low Power Current Mode Up-Conversion Mixer for 5G Application. IETE Journal of Research. 2022;1(13):1–13. Available from: https://doi.org/10.1080/03772063.2022.2103039
  17. Saritha M, Lavanya M, Ajitha G, Reddy MN, Annapurna P, Sreevani M, et al. A VLSI design of clock gated technique based ADC lock-in amplifier. International Journal of System Assurance Engineering and Management. 2022;13(5):2743–2750. Available from: https://doi.org/10.1007/s13198-022-01747-6


© 2023 Shukla et al. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. Published By Indian Society for Education and Environment (iSee)


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