Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 33, Pages: 1-6
M. Hanumanthu* , N. Bala Dastagiri, B. Abdul Rahim and P. Somasundar
Department of Electronics and Communication Engineering, Annamacharya Institute of Technology and Sciences, Rajampet - 516126, Andhra Pradesh, India; [email protected]
*Author for correspondence
Department of Electronics and Communication
Background/Objective: To design the AND, OR type circuits based on foot based and foot-less based gate domino logic and compare the results. Methods/Statistics: Nowadays VLSI circuits are expected to operate with low power, high speed, less area and noise tolerance. The major challenge in VLSI circuits is to obtain high performance. There are several digital logic techniques available viz. pseudo static CMOS, pass-transistor logic, complementary pass-transistor logic, GDI, dynamic CMOS logic, domino CMOS logic, which can be used to achieve high performance circuits. Findings: Static CMOS circuits have both pull down and pull up networks, but the disadvantage is, total number of transistors in the circuit is more. The dynamic logic circuits overcome the disadvantage of static complementary MOS. On the other side dynamic logic suffers from charge leakage, charge sharing and noise sensitivity, due to sub-threshold leakage current flow in the Pull Down Network (PDN), called stacking effect. When we scale down the technology, these effects will also get increased.
Keywords: Footed, Foot-Less Domino, Power Dissipation
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