• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2016, Volume: 9, Issue: 16, Pages: 1-5

Original Article

Design and Implementation of the Combinational Circuits Testing using Accumulator based BIST to Reduce Delay, Power Consumption and Area


Background: In Current VLSI circuits, e.g., Modules likeaccumulators, Arithmetic Logic Units (ALUs) are present generally in information linestructure or discrete signal Processing chips. ABIST has a basic idea that is used by accumulators for built-in testing and itsgenerated test patterns show the hardware overhead degradation and decreased circuit speed. Method:In the present system this paper use a scheme which holds a generation of test patterns and is compared with previously proposed scheme. The test patterns created by accumulator proves that it takes input produced by a constant pattern holding an acceptable pseudorandom individuality, if a proper input pattern is selected.Weighed pseudorandom BISTschemes were utilized to bring down the vector number in BIST applications.Findings:For the generation of test patterns, we use a group which has 0, 1 and 0.5 weights and this group is an impartial group and this use will lower the time needed for testing and also reduces power used. In the above work, digital circuits such as G27 Bench mark and SISO are, accumulator based BIST. Finally, the synthesis results of these circuits are compared with normal BIST. It was found that the circuit as low delay using accumulator based BIST.

Keywords:ABIST, ALU, BIST, CUT, Combinational Circuits


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