Indian Journal of Science and Technology
Year: 2019, Volume: 12, Issue: 43, Pages: 1-4
Dr. Ayyavoo Mithila*, A. Lavanya, A.R. Nithyashree and T.R. Mithra
Objective: To design and implement flash ADC for high speed operation thereby to minimise the power consumption and improve the performance efficiency. Methods: At present, there exists a variety of Analog-to-Digital Converter (ADC) with different architecture, sampling rates, resolutions, temperature ranges, and power consumption. The existing ADCs used in various multiple applications which include mobile communication hardware to measuring instruments. Therefore, their significant performance and working of ADCs are determined by its architecture, the commonly existing ADC design is not suitable for all applications. In order to meet the high speed operation scenario, a Flash type ADC model is proposed. Findings: Resistor ladder would be commonly used in all type of ADC circuits, but downside it consume maximum area and power. In all existing methods, the average power consumption of Flash ADC is found to be higher when compared with our methodology. This can be overcome by using threshold inverting quantization (TIQ) comparator for low power operation. Improvements: An efficient thermometer to the binary code converter is targeted for 45 nm CMOS technology that has been proposed and implemented Flash CMOS ADC Design using the CADENCE VIRTUOSO Tool. The optimal power analysis has been carried out to prove the design absolutely a low power model.
Keywords: Flash ADC, Low Power, CMOS Technology, TIQ Comparator, CADENCE VIRTUOSO
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