• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2015, Volume: 8, Issue: 32, Pages: 1-7

Original Article

Design of Novel Low Power Dual Edge Triggered Flipflop


Low power designs are gaining more importance in the recent VLSI Era. Electronics Design Automation (EDA) tools play a vital role in low power system implementation. High speed Computing and processing applications also requires low power designs to enhance their performance. Flip-flops are the basic memory and timing elements in digital circuits. To improve the performance of digital circuits new methods have to be devised for the implementation of low power and energy efficient flipflops. This in turn will help to improve the speed and performance of the system. This paper aims in the design of novel low power flip-flop which is an important element to determine the performance of the synchronous circuit in the area of low power VLSI.


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