Indian Journal of Science and Technology
Year: 2015, Volume: 8, Issue: 32, Pages: 1-6
M. Jasmin1*. T. Vigneshwaran2 and S. Beulah Hemalatha1
Department of ECE, BharathUniversity, Chennai - 600073, Tamil Nadu, India; [email protected], [email protected]
2 School of Electronics, VITUniversity, Chennai - 600127, Tamil Nadu, India; [email protected]
A new design methodology to reduce power consumption and minimization of area in FSM based system is fore fronted into FPGA using Finite State Machines (FSMs) mapping in this proposed work. This FSM is mapped into the On Chip Embedded Memory (OCEM) through clock gating technique. FSM encoding is stored using OCEM as it reduces the Flip-Flop (FF) and combinational function usage. Clock gating technique will reduce the power consumption additionally through blocking the clock while OCEMP is inidle state. The proposed design is tested and analyzed using ALTERA cyclone II FPGA for Arithmetic Logic Units(ALU), Advanced Encryption Standard core (AES), SRAM controller and Synchronous FIFO. OCEM based implementation of One- Hot encoding is performed and compared with conventional Flip-Flop based Onehot encoding and analyzed.The FSM implemented using proposed method consumes less power and fewer areas when compared with FF based FSM implementation or using binary encoding technique. The OCEM based implementation can be clocked to maximum clock frequency. Experimental results and analyses shows that OCEMbased FSM consumes 4 to 26 % less power than FF based techniques.
Keywords: Gated Clock, Low Power Design, Synchronous Counter
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