Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 13, Pages: 1-5
P. Michael Preetam Raj, Bhaskaruni Sandeep* , D. Sai Mallik Reddy, P. Ramanjaneyulu and Sakhamuri Sai Pravallika
Department of Electronics and Communication Engineering, KL University, Guntur - 522502, Andhra Pradesh, India; [email protected], [email protected], [email protected], [email protected], [email protected]
*Author for correspondence
Department of Electronics and Communication Engineering, KL University, Guntur - 522502, Andhra Pradesh, India; [email protected]
Objective: VLSI integer adders are critical elements in general purposed DSP and DSPA processors. These used in design of ALU, floating point arithmetic data paths and address generation units. Parallel prefix adders rely on simple cell design. Modern FPGAs utilize fast carry chain for optimization ripple carry adder. Methods/Analysis: Design of the delay models and cost analysis by VLSI embedded system is done in this paper. Prefix adder with reversible logic gates utilizing 16 bit kogge stone adder have been design using PERES logic. Findings: Methodology is based on the fact that a parallel prefix adder can be represented as a graph consists of carry operator nodes. The adder structure has minimum logic depth and binary tree structure with minimum fan-out. From the simulate results this is formed that computational path net delay for 16 X16 bit prefix adder using reversible logic is 20.828 ns with Kogge Stone Adder is reading to 17.247ns. Novelty/ Improvement: The multiple based on 16 bit Kogge Stone Adder is formed to be less efficient than the case of reversible adder in term of delay and power analysis.
Keywords: Kogge Stone Adder, Logic Gates, Prefix Adder, Peres Gate, Reversible Logic Gate
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