Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 13, Pages: 1-10
Suryasnata Tripathy1 , Sushanta K. Mandal2 , B. Shivalal Patro1* and L. B. Omprakash1
1KIIT University, Bhubaneswar – 751024, Odisha, India; [email protected], [email protected] gmail.com, [email protected] gmail.com 2CUTM, Paralakhemundi – 761211, Odisha, India; [email protected]
*Author of Corresponding: B. Shivalal Patro KIIT University, Bhubaneswar – 751024, Odisha, India; [email protected] gmail.com
Design of a high speed magnitude comparator with minimal power consumption is essential for addressing the ever growing need of real time signal processing and data acquisition. Simultaneous optimization of speed and power constraints is the major design bottleneck associated with digital datapath design for higher word length processors. In this work, a novel architecture for 8-bit digital comparator is proposed which is directed at high speed signal processing without incurring significant power consumption. The principle of Parallelism has been successfully employed in the proposed architecture for reduction of overall power consumption without affecting the speed. The 8-bit comparator unit is realized using three different 1-bit comparator architectures proposed in this study and their performance analysis is carried out using several combinations of input vectors. The proposed topology is designed using pass transistor logic, static CMOS logic and transmission gate based logic which accounts for the improved performance metric as compared to the more commonly employed dynamic CMOS logic based designs due to relatively smaller data activity factor. The architecture is designed in 45 nm standard CMOS Process technology using Cadence EDA tool. The introduction of parallelism and use of modified 1-bit comparator topologies significantly lower the overall power consumption along with increasing the processing speed. The proposed design achieves average power dissipation of 196 nW and propagation delay of 129 pS for a power supply voltage of 1 volt. Performance metric associated with the proposed design shows a significant improvement in performance over similar architectures reported earlier in literature. Further improvement in performance can be achieved by introducing higher degree of parallelism into the proposed architectures.
Keywords: Comparator, Dynamic CMOS Logic, High Speed, Low Power, Pass Transistor Logic, Static CMOS Logic, Transmission Gate Based Logic
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