Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 32, Pages: 1-7
Akash Punhani1*, Pardeep Kumar1 and Nitin2
1 Department of CSE and IT, Jaypee University of Information Technology, Waknaghat, Solan-173234, Himachal Pradesh, India; [email protected]
2 Department of CSE and IT, Jaypee Institute of Information Technology, A-10, Sector-62, Noida-201307, Uttar Pradesh, India; [email protected]
*Author for correspondence
Department of CSE and IT
Objectives: The high computing demands leads to high communication between the various cores on the chips. This leads to the exploration of various topologies. The Mesh based topologies are widely accepted due to simplicity. This mesh topology is modified with objective to reduce inter node distance. Methods/Statistical Analysis: Proposed topology has been generated as the union of the Diagonal connected mesh and T Mesh. To test the performance the proposed topology that is Diagonal connected T mesh is compared with diagonal connected mesh and T Mesh. To test the performance of the topology static routing algorithm is used. The various traffic patterns have been used for the analysis of latency and bandwidth. Findings: The proposed topology has performed better in comparison to Diagonal connected Mesh and T Mesh in case of Uniform traffic and Bit Complement traffic. In case of tornado traffic results are identical to that of Diagonal connected mesh. The hop count analysis shows that there is always a positive improvement. Average Hop count of the diagonal Connected T mesh is 87% less than that of it counterpart. This makes the proposed proved to be better than the existing topologies. Application/Improvements: The proposed topology for network on chip will always be suitable for the applications in which the communication is either uniform among the nodes or is communicating to the nodes having complement traffic match.
Keywords: Hop Count, Mesh, Network on Chip, Topology, Traffic Analysis
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