Digital Circuit Design using Chaotic Particle Swarm Optimization Assisted by Genetic Algorithm

Hamid Reza Nikoui  and Mohadeseh Semsari

doi:10.17485/ijst/2013/v6i9.4

Article

VIEWS 779
PDF 332

Abstract
Full-Text HTML
Full-Text PDF
How to Cite

Indian Journal of Science and Technology

DOI: 10.17485/ijst/2013/v6i9.4

Year: 2013, Volume: 6, Issue: 9, Pages: 1-7

Original Article

Digital Circuit Design using Chaotic Particle Swarm Optimization Assisted by Genetic Algorithm

Hamid Reza Nikoui^* and Mohadeseh Semsari

Department of Electronic Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran; [email protected]
*Author For Correspondence
Hamid Reza Nikoui
Department of Electronic Engineering
Email:[email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

Optimal digital circuit design could be very beneficial for reducing the expenses of electronic devices. But since it is a complicated problem in general, utilization of sophisticated algorithm for this task seems necessary. In this paper a new method based on combining particle swarm optimization, genetic algorithm and chaotic search is proposed for digital circuit design. The inclusion of wiring minimization in objective function is also proposed and investigated.
Keywords: Digital Circuits, Particle Swarm Optimization, Genetic Algorithm, Chaotic Local Search, Wiring Minimization.