• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2016, Volume: 9, Issue: 29, Pages: 1-5

Original Article

Digital Infinite Impulse Response Filter with Floating Point Multiply Accumulate Circuit using Pipelining


A competent architecture for IIR filter is designed. It is configured and folded, which will be used in the real time applications like loud speaker and equalization of digital signal processing. A basic feature of digital signal processing is filtering. Filtering is a choosy system which passes an assured choice of frequency and attenuating the others frequency. Digital filtering is a prevailing sector of DSP allied works. A system of digital filter performs mathematical operations on a sampled or discrete time variant signal to contract or improve certain aspects of that signal. The configurable folded IIR filter for sixth order is designed using three series of second order IIR filter. This IIR filter architecture is used to carry out three second order or a one sixth order. It can be also used to execute one fourth order and one second order in parallel according to the requirement where, each second order IIR filter is designed using multiply accumulate circuit which as floating point. Here pipelining of IIR filter for second order is proposed to increase the throughput by reducing the critical path delay. The proposed sixth order IIR filter using three second order IIR filter with pipelining achieves 39.7% of increased throughput and it operates at high frequency of 85.068MHz compared with conventional MAC based architecture
Keywords: IIR Filter, Multiply Accumulate Circuit (MAC), Pipeline


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