Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: Special Issue 1, Pages: 1-6
S. E. Mathe and L. Boppana
Department of Electronics and Communication Engineering, National Institute of Technology, Warangal – 506004, Telangana, India; [email protected]
Objectives: Multiplication in Galois fields is used in many applications, especially in cryptography. Several algorithms and architectures are proposed in the literature to obtain efficient multiplication operations in Galois fields. Methods/ Statistical Analysis: In this paper, based on a modified interleaved modular multiplication algorithm, a bit-parallel systolic multiplier based on generic irreducible polynomials over Galois Field (GF (28 )) is proposed. Theoretical hardware and speed complexity analysis is performed and the proposed multiplier is compared with other systolic multipliers available in the literature for irreducible polynomials. Findings: The proposed systolic multiplier achieves 21.23% reduction in hardware complexity when compared with the best multiplier among existing multipliers for m = 8. Applications/Improvements: The Field-Programmable Gate Array (FPGA) implementation results for the Advanced Encryption Standard (AES) and Two fish algorithms, incorporating the proposed multiplier and some existing designs, are also presented which indicates that the proposed multiplier achieves low area and low power consumption when compared with other systolic multipliers available in the literature.
Keywords: Bit-Parallel, Cryptography, Field Programmable Gate Arrays, Galois Field, Polynomial Basis, Systolic
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