Indian Journal of Science and Technology
Year: 2015, Volume: 8, Issue: 17, Pages: 1-6
Sweety1* , Minal Dhankar1 , Ravinder S. Kajal 1 , Kartik Kalia2 , Kushagra Vashishta2 and Amit Kumar3
1 Department of Computer Science, Maharaja Surajmal Institute, Janakpuri, Delhi-110058, India; [email protected]
2 Department of ECE, Chitkara University, Punjab - 140 401, India 3 Department of IT, IIIT Gwalior, Gwalior, India
In this work, we are designing a energy efficient memory circuit on 28nm FPGA. Four different LVCMOS are used to validate the energy efficient design. There is 40.67% power reduction when LVCMOS25 is used in place of LVCMOS33. LVCMOS25 is better than LVCMOS33 IO Standard according to our experiment. With LVCMOS15 there is 75.70% total power reduction in compare with the LVCMOS33. LVCMOS15 is most energy efficient IO Standard and LVCMOS33 is most power consuming IO Standard. To design a power efficient memory we are using Verilog as HDL, Xilinx ISE 14.6 simulator with kintex-7 FPGA.
Keywords: Energy Efficient, FPGA, IO Standard, Low Power, LVCMOS, Memory
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