Energy Efficient Memory Design using Low Voltage Complementary Metal Oxide Semiconductor on 28nm FPGA

Sweety; Minal Dhankar; Ravinder S  Kajal; Kartik Kalia; Kushagra Vashishta  and Amit Kumar

doi:10.17485/ijst/2015/v8i17/76237

Article

Energy Efficient Memory Design using Low Voltage Complementary Metal Oxide Semiconductor on 28nm FPGA

VIEWS 740
PDF 362

Abstract
Full-Text HTML
Full-Text PDF
How to Cite

Indian Journal of Science and Technology

DOI: 10.17485/ijst/2015/v8i17/76237

Year: 2015, Volume: 8, Issue: 17, Pages: 1-6

Original Article

Energy Efficient Memory Design using Low Voltage Complementary Metal Oxide Semiconductor on 28nm FPGA

Sweety^1* , Minal Dhankar¹ , Ravinder S. Kajal ¹ , Kartik Kalia² , Kushagra Vashishta² and Amit Kumar³

¹Department of Computer Science, Maharaja Surajmal Institute, Janakpuri, Delhi-110058, India; [email protected]
² Department of ECE, Chitkara University, Punjab - 140 401, India 3 Department of IT, IIIT Gwalior, Gwalior, India

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

In this work, we are designing a energy efficient memory circuit on 28nm FPGA. Four different LVCMOS are used to validate the energy efficient design. There is 40.67% power reduction when LVCMOS25 is used in place of LVCMOS33. LVCMOS25 is better than LVCMOS33 IO Standard according to our experiment. With LVCMOS15 there is 75.70% total power reduction in compare with the LVCMOS33. LVCMOS15 is most energy efficient IO Standard and LVCMOS33 is most power consuming IO Standard. To design a power efficient memory we are using Verilog as HDL, Xilinx ISE 14.6 simulator with kintex-7 FPGA.
Keywords: Energy Efficient, FPGA, IO Standard, Low Power, LVCMOS, Memory