Indian Journal of Science and Technology
DOI: 10.17485/ijst/2015/v8i33/76080
Year: 2015, Volume: 8, Issue: 33, Pages: 1-8
Original Article
Mohammed Altaf Ahmed1*, D. Elizabeth Rani1 and Syed Abdul Sattar2
1GITAM Institute of Technology, GITAM University, Visakhapatnam – 531173, Andhra Pradesh, India; [email protected], [email protected]; [email protected]
2 Royal Institute of Technology and Science, Chevella – 501503, Andhra Pradesh, India; [email protected]
In the current high speed, low power VLSI Technology design, Built in Self Test (BIST) is emerging as the most essential part of System on Chip (SoC). The industries are flooded with diverse algorithms to test memories for faults. The March based algorithms are become popular so quickly for locating faults in memories. This research study attempt to design the memory BIST controller for March 17N as selected algorithm. It tests various memories for faults. A simple architecture is implemented in Verilog Hardware Description Language (HDL), which can be easily integrate with SoC and is able to locate the fault location in the semiconductor memories. Integration of memory BIST controller in SoC design improves chip yield. The design has achieved 497.47MHzof maximum frequency by use of only 158 slice LUTs on Virtex-7 Field Programming Gate Array (FPGA) device. The proposed memory BIST controller is suitable for SoC integration to test various memories at high speed with very low area overhead.
Keywords: Low Area, Memory BIST, SoC Integration, Test Memories, Yield Improvement
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