Indian Journal of Science and Technology

Abstract

Sigma delta ADC is mainly used in resolution based application. But the gain of the sigma delta modulator is low. The main objective of the paper is to design the comparator with high gain. Comparator with low gain cannot drive the load effectively through the entire circuit. This paper was designed and simulated using 180 nm process technology (GPDK 180 nm library) in CADENCE Virtuoso Analog Design Environment. In sigma delta ADC, each block should drive the load effectively to the entire circuit. So that the output will come accurately and delay will be less. Based on that concept, need to design the comparator that can be used in sigma delta ADC. In this point of view, some comparators are analysed. In this paper, analyse the performance of regenerative comparators and op-amp based comparators. And find which will efficient comparator for using at sigma delta modulator. Dynamic comparator, double tail comparator, modified double tail comparator are analysed. The gain of these operational amplifiers are low. So high gain based operational amplifier should be designed. For that, first one op-amp was designed which has 84 dB gain. Using this opamp, one comparator was designed. This comparator has high gain. So it can be used for sigma delta ADC for drive the load. And also it meets certain other constraints like speed and moderate power.
Keywords: CMOS, Opamp Based Comparator, Regenerative Comparators, Sigma Delta ADC, UDSM CMOS Technology