Indian Journal of Science and Technology
DOI: 10.17485/ijst/2016/v9i33/99516
Year: 2016, Volume: 9, Issue: 33, Pages: 1-5
Original Article
Manisha Guduri* , Amit Krishna Dwivedi, and Aminul Islam
Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi - 835215, Jharkhand, India; [email protected]
[email protected]
[email protected]
*Author for correspondence
Manisha Guduri
Department of Electronics and Communication Engineering
Email: [email protected]
Objectives: The objective of this research paper is to design High Vt-Low Leakage FDSOI Device for Ultra-Low Power Operation. Methods/Analysis: This research work presents the modeling of fully depleted silicon on insulator (FDSOI) device with 350-nm gate length. This paper investigates threshold voltage (Vt) and leakage power of the different FDSOI devices in order to design high threshold voltage and low leakage device. Findings: It is observed that device5 shows higher Vt and dissipates lower leakage power when compared to that of other devices (devices1−4). The threshold voltage and subthreshold slope (SS) of device5 are observed to be 0.199 V (~0.2 V) and 80 mV/decade respectively. The leakage power of the device at drain voltage of 1 V is 41.9 nW. Novelty /Improvement: This kind of FDSOI device is a platform for designing circuits at nano scale regime for ultra-low power applications.
Keywords: FDSOI Device, Leakage Power, Threshold Voltage, Subthreshold Slope
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