Indian Journal of Science and Technology
DOI: 10.17485/ijst/2016/v9i5/87181
Year: 2016, Volume: 9, Issue: 5, Pages: 1-8
Original Article
G . Ragunath* and R. Sakthivel
VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, India; [email protected], [email protected]
*Author For Correspondence
G . Ragunath VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, India; [email protected]
Background/Objectives: XOR gate is a primary element in binary adders because which is used to detect sum – output. In this paper a 2-input XOR gate is accomplished by a modified design. Methods/Statistical Analysis: Usually a Half Adder (HA) circuit is designed with one XOR and one AND gate but if this modified XOR is used in HA, the design requires only one XOR gate and the AND gate can be acquired from XOR gate itself. Findings: This modified XOR gate design gives better result when the adder circuit has more number of XOR gates, so we used this modified XOR gate in conventional sqrt CSLA, Binary to Excess-1 Converter (BEC) based sqrt CSLA and Optimized Logic Based (OLB) sqrt CSLA. The results show that Area – Delay – Product (ADP) has been reduced in proposed circuits, 12.45% in conventional sqrt CSLA, 21.45% in BEC based sqrt CSLA and 17.81% in OLB sqrt CSLA. Applications/Improvements: These adders can be used in Arithmetic Logic Unit (ALU) of a micro-processor as a binary adder.
Keywords: Application Specific Integrated Circuits (ASIC), Area Efficient, Low Power, Sqrt CSLA, XOR Gate
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