Indian Journal of Science and Technology
Year: 2015, Volume: 8, Issue: 17, Pages: 1-6
Gaurav Verma* , Manish Kumar and Vijay Khare
Department of Electronics and Communication, Jaypee Institute of Information Technology, A-10, Sector-62, Noida - 201307, Uttar Pradesh, India;
[email protected], [email protected], vijay.kumar.jiit.ac.in
The proliferation of reconfigurable hardware like (FPGAs) put a challenge in front of designers to implement fast and low powered digital designs. Main drawbacks of FPGAs are the complex circuitry which makes them less efficient as compared to ASIC (Application Specific Integrated Circuits). Although appropriate to scaling in CMOS technology reduce the power required for performing the known job, it increase clout indulgence for each part of region. At similar instant request of low power application is swelling due to increase of smart devices and increasing energy costs. Since power consumption is an extremely significant issue in digital classification of designs, so the authors have presented and analyzed some power reduction techniques that can be targeted at different levels of design hierarchy for different target platform. The authors would also discuss concept of ACPI module designed for newer operating systems, which provides basic power management facilities to save system power.
Keywords: ACPI, Clock Tree, Flattening and Factorization, Low Uncertainty Clock Tree (LUCT)
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