Indian Journal of Science and Technology

Abstract

Objectives: In this paper, a systematic analysis is done on existing logical architecture of on-chip data transmission for a digital integrated circuit like System-on-a-Chip (SoC), Network on Chip (NoC), etc. for fast data communications. Analysis: For systematic comparisons, buses are categorized in different topology based on logical architectures and in the different protocol depending on their communication mechanism. The paper illustrates the operation of the arbiter mechanism. The paper present a systematic analysis of the topology and protocols based on sequential data transmission methods, the priority of accession mode, flexibility and compatibility and performance analysis for the cases of different logic structures and clock frequencies. Finding: Multiple buses are suitable to connect maximum number blocks to avoid the overloading effect on a single bus. The Matrix bus seems to be the best solution for attaining high-speed block data communication, but not energy efficient where as share bus is the most energy efficient bus but not suitable for high-speed operation. Several existing On-Chip Communication Architecture (OCBCA) in the literature and compare them according to their structure, advantages, limitations and application criteria to achieve full performance by minimized logical constituent and the different functional blocks using different communication channels and interconnections. Novelty: Comparison among the all existing on-chip interconnection topology, protocols and minimization techniques of logical constituents. 

Keywords: Arbiter, Embedded Cores-Based System-on-a-Chip, High-Speed Data Transmission, Logical Architecture, On-Chip Bus Communication Architecture, On-Chip Bus Protocols, The Sequential Operation of the On-Chip Bus