Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: Special Issue 1, Pages: 1-6
Abeera Dutt Roy* and Chandrahasan Umayal
School of Electrical Engineering, VIT University, Chennai – 600127, Tamil Nadu, India; [email protected]
*Author for correspondence
Abeera Dutt Roy
School of Electrical Engineering
Email: [email protected]
Objective: In this paper, the detailed analysis and performance of a single phase multilevel inverter topology is dicussed in order to produce a high quality of output voltage. Method: A seven level cascaded inverter topology having six switches is utilized to reduce the total harmonic distortion and the switching losses. This in turn reduces the overall cost of the system. The comparison between the proposed architecture and the existing architectures is done based on the power switches, DC voltage at the inputs, the number of clamping diodes and capacitors used. It is observed that the switch count is halved. Findings: Evaluation is done using phase disposition multicarrier pulse width modulation technique where all the carriers are in phase. Thus this technique is found to be capable of achieving minimum harmonic voltage distortion, thereby resulting in a nearly sinusoidal waveform. Improvements: The performance of the suggested topology is validated in real time environment using Opal-RT Lab simulator and adequate results were taken. The results obtained proved that by using lesser number of switches there is reduction in harmonic voltage distortion in comparison with the traditional multilevel inverter topologies.
Keywords: Cascaded Multilevel Inverter, Multicarrier Pulse Width Modulation, Opal-RT, Sinusoidal Waveform, Total Harmonic Distortion
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