Indian Journal of Science and Technology

Abstract

Objectives: To design the 16bit Reduced Instruction Set Computing (RISC) processor using the Verilog Hardware Description Language (HDL). Methods: This is a 4 stage pipelined processor with idle state, fetch state, decode state, and execute state. Here the write back stage is also performed in the same execution state. The physical design of the processor is done by floor plan followed by placement and routing process. In the placement process iteration is continued till it meet the timing constraints. Findings: In the floor plan we decide the utilization factor, width and height of the core and die, apart from that we decide the location of the IO Pads. The location of the preplaced cells and standard cell placement are find during the placement process. In the placement process if the congestion is huge then the hard blockage placement is done to eliminate the congestion. During the trail route the tool does the timing analysis using the ideal clock, which is then replaces the ideal clock with the real clock after the clock tree synthesis. This process is followed by the spare cells placement in the empty region where we can replace these cells with the logic cells in future; this step in the physical design procedure is known as Engineering Change Order (ECO). During the tape out process if the timing is not met we may not do the placement and routing process from the starting step so we go for the ECO where we can replace the cells with the other cells of same functionality to reduce the delay in order to remove the setup slack. Applications: RISC processors are used in wide range of applications such as mobile phone, tablet computer, super computers etc, RISC processors are also used in signal processing applications such as convolution, correlation etc.
Keywords: Engineering Change Order (ECO), Pipelined Architecture, RISC Processor