Indian Journal of Science and Technology
DOI: 10.17485/ijst/2016/v9i37/102139
Year: 2016, Volume: 9, Issue: 37, Pages: 1-5
Original Article
Deepa Divakar*and V.Arunachalam
Department of Micro and Nanoelectronics, VIT University, Vellore - 632014, Tamil Nadu, India; [email protected]
[email protected]
*Author for correspondence
Deepa Divakar
Department of Micro and Nanoelectronics
Email: [email protected]
Objectives: An algorithm is proposed to allocate the scan cells to form a particular set of scan chains. The proposed algorithm reduces wire length and number of multi-voltage cells. This also maintains the balance of the chain. Methods: The proposed algorithm was implemented in Tool Command Language (TCL) and it works on the post placed database. The developed algorithm was tested on some of the industrial designs. Findings: The proposed algorithm was tested on some of the industrial designs and a reduction was observed in the scan chains wire length (about 10%) and a much greater reduction in the count of the lockup latches (about 90%). Improvements/Applications: This will ensure a reduction in congestion as well as reduced area requirements.
Keywords: Design for Testability (DFT), Multi-Domain Mixing, Scan Allocation, Scan Segments
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