Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 28, Pages: 1-7
Nidamanuri Sai Charan* and Kakarla Hari Kishore
Department of ECE, K L University, [email protected]
*Author for correspondence
Nidamanuri Sai Charan
Department of ECE, K L University,
Email: [email protected]
This paper discussed about the increasing complexity of Field-Programmable Gate Array (FPGA) in finding delay faults using BIST technique. It is a major challenge for FPGA for highest troubles shoot text and delay circuit quickly. Built-inself-test method is a simple solution compared with expensive test equipment for the automatic transmission. Herein, the erection designed for the detection of delay faults in the second coefficient of FPGA resources Digital Signal Processing (DSP) block, FPGA board interconnects, Look-Up-Tables (LUT) and etc. The authors suggest comprehensive plan diagnose Bister to improve the effectiveness of the control logic, which diagnose all CLB 2 x 3 BIST are faulty. The overall process for the simulation has been done by tool Xilinx FPGA Vertex FPGA. The results show a significant improvement over previous methods.
Keyword: BIST, CLB, Delay Fault, FPGA, LUT, ORA
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