Indian Journal of Science and Technology
Year: 2008, Volume: 1, Issue: 3, Pages: 1-4
B. I. Neelgar, Prabhu. G. Benakop*
G.M.R. Institute of Technology, Rajam-532127, Andhra Pradesh, India
*Aurora Engineering College, Bhongir-508116 Andhra Pradesh, India
*Author for the correspondence:
Prabhu. G. Benakop
Aurora Engineering College, Bhongir-508116 Andhra Pradesh, India
E-mail: [email protected]
In this paper, an attempt is made to reduce the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. The basic idea is to assign multiple codes to states so as to enable more effective clock gating in the sequential circuit. Experimental results demonstrate that the priority encoding technique can result in sizable power saving.
Keywords: priority encoding, multi code state assignment, clock gating.
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