Indian Journal of Science and Technology

Abstract

Objectives: The scaling down of CMOS technology feature size may bring out many benefits in terms of area, performance, cost etc., but the undesirable effects such as variability in the parameters of the circuit and operating environment are increasing which in turn leads to uncertainty in the circuit performance and lowering of yield. In this study, the impact of variations has been analyzed, on the delay of standard cells. It is necessary to model variations to predict the performance. Methods: This analysis is performed by different Variation modeling techniques for Standard Cell Characterization. The Monte Carlo technique introduces randomness by changing the threshold voltage such that it is different for different transistors at the same time. In contrast, Liberty Variation Format used for lower technologies, gives the variation of a cell delay at 1 sigma of delay distribution per arc which covers all slew-load, arc and when conditions. Findings: The delay for every cell varies based on the active arc/input transition/output load. After running the simulations for Cell a using Monte Carlo and Liberty Variation Format technique, the result and delay spread for Monte Carlo simulations is obtained which is compared with the standard deviation values from the Liberty Variation Format simulations. After comparing them we can see the values almost tend to be equal. This way instead of running the Monte Carlo Simulations, which have a huge runtime we can also obtain the accurate standard deviation (sigma) values from the Liberty Variation Format simulations. Application: The simulation results demonstrate the variation in the delay of those cells from the nominal value and which modeling technique can be used for efficient Variation calculation for circuit parameters.

Keywords: Liberty Variation Format, Monte Carlo Simulations, Process Variations, Standard Cells, Variations