Indian Journal of Science and Technology

Abstract

The advent of dynamic logic especially domino logic has made the use of dynamic circuits very wide for the implementation of low power VLSI circuits. Dynamic logic style is becoming the designers’ choice these days because it has very fast speed and occupies very small area. In this paper we have used various techniques based on domino logic to overcome noise. Each technique has its merits and demerits. Out of these techniques mentioned below we have taken two widely used techniques in domino logic, conditional keeper technique and diode footed domino. We calculated their noise margins at different values of supply voltage. We have done simulations in 90 nm technology. After calculations we found both techniques show fairly good noise immunity but diode footed domino gave better results.
Keywords: Delay, Diode Footed Domino, Immunity, Leakage Tolerance, Noise, Power Consumption, Subthreshold Voltage, Technology Scaling