12-Bit Clock Gated SAR-ADC for Bio-Medical Applications

Jyoti Sehgal; Manoj Kumar

doi:10.17485/IJST/v15i34.1033

Article

12-Bit Clock Gated SAR-ADC for Bio-Medical Applications

VIEWS 1108
PDF 193

Indian Journal of Science and Technology

DOI: 10.17485/IJST/v15i34.1033

Year: 2022, Volume: 15, Issue: 34, Pages: 1648-1654

Original Article

12-Bit Clock Gated SAR-ADC for Bio-Medical Applications

Jyoti Sehgal^1*, Manoj Kumar²

¹Research Scholar, UIET, MDU, Rohtak, Haryana, India
²Assistant Professor, UIET, MDU, Rohtak, Haryana, India

*Corresponding Author
Email: [email protected]

Received Date:15 May 2022, Accepted Date:15 July 2022, Published Date:27 August 2022

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

Background/Objectives: Power optimization is a critical design criterion in modern integrated circuits. The unwanted clock signals are neutralized and the reduction in power consumption is made presumable by using the clock gating technique. Methods: Analog-to-digital converters (ADCs) are important components in these systems. A widely used successive approximation register A/D converter includes an internal clock, reference, and high resolution. The number of redundant cycles is increased with improved resolutions but enhances the consumption of power. Thus, the clock gating strategy is used to substantially lower the circuit’s dynamic power consumption. The clock gating technique is implemented with a reduced number of transistors to minimize the overhead with high switching activity. Also, demonstrate no imperfection on the clock duty cycle. Findings: A 12-bit clock gated SAR register using a D-flip flop with 1.8 V supply voltage is proposed in this study for efficient biomedical applications. SAR without a clock gating technique consumes 54 mW of power and SAR with a clock gating technique consumes a power of 22.68 mW. Novelty: The clock gating technique is stipulated to minimize power consumption of clock gated SAR-ADC and improves the battery life of the portable device.

Keywords: Clock gated technique; power consumption; resolution; SARADC; successive approximation register

References

Chindhu ST, Shanmugasundaram N. Clock Gating Techniques: An Overview. 2018 Conference on Emerging Devices and Smart Systems (ICEDSS). 2018;p. 217–221.
Limotyraskis S, Kulchychi SD, Su D, Wooley BA. A 150MS/s 8b 71mW time-interleaved ADC in 0.180µm CMOS. In: Proc. IEEE Int. Solid-State Circuits Conference Dig. Tech papers. (pp. 258-259) 2004.
Soliman A, Mahmoud, Salem HA, Albalooshi HM. ”An 8-bit, 10KS/s, 1.87µW Successive approximation analog to digital converter in 0.25µm CMOS technology for ECG detection systems. Proceeding of the circuits, systems, and Signal Processing. 2015;34. Available from: https://doi.org/10.1007/s00034-015-9973-z
Martin J, Kramer E, Janssen K, Doris B, Murmann. A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS. IEEE Journal of Solid-State Circuits. 2015;50(12):2891–2900. Available from: https://doi.org/10.1109/JSSC.2015.2463110
Alpman E, Lakdawala LRH, Carley K, Soumyanath. A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS. In: 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers. (Vol. 77, pp. 76-77) 2009. https://doi.org/10.1109/ISSCC.2009.4977315
Chen SWM, Brodersen RW. A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-CMOS. IEEE Journal of Solid-State Circuits. 2006;41(12):2669–2680. Available from: https://doi.org/10.1109/JSSC.2006.884231
Cao Z, Yan S, Li Y. A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13-CMOS. IEEE Journal of Solid-State Circuits. 2009;44(3):862–873. Available from: https://doi.org/10.1109/JSSC.2008.2012329
Shaker MO, Bayoumi MA. A clock gated flip-flop for low power applications in 90 nm CMOS. 2011 IEEE International Symposium of Circuits and Systems (ISCAS). 2011;p. 558–562. Available from: 10.1109/ISCAS.2011.5937626
Shaker MO, Bayoumi MA. A clock gated Successive approximation register for A/D conversions. Journal of circuits, systems, and computers. 2014. Available from: https://doi.org/10.1142/S0218126614500236
Shaker MO, Bayoumi M. Novel clock gating techniques for low power flip-flops and its applications. 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS). 2013;p. 420–424. Available from: https://doi.org/10.1109/MWSCAS.2013.6674675
Anderson TO. Optimum control logic for Successive Approximation Analog to Digital converters. Computer Design. 1972;11:81–86.
Rossi A, Fucili G. Nonredundant successive approximation register for A/D converters. Electronics Letters. 1996;32(12):1055.
Strollo AGM, Napoli E, Caro DD. New clock-gating techniques for low-power flip-flops. Proceedings of the 2000 international symposium on Low power electronics and design - ISLPED '00. 2000;p. 114–119. Available from: https://doi.org/10.1145/344166.344540
Strollo AGM, Napoli E, Caro DD. Low-power flip-flops with reliable clock gating. Microelectronics Journal. 2001;32(1):21–28. Available from: https://doi.org/10.1016/S0026-2692(00)00072-0
Kumar M, Kumar R. A Ultra Low Power 12 Bit Successive Approximation Register for Bio-Medical Applications. International Journal of Engineering & Technology. 2018;7(3.16):98.
Srinivasan N, Prakash NS, Shalakha D, Sivaranjani D, Lakshmi GSS, B. Bala Tripura Sundari, Power Reduction by Clock Gating Technique. 2015;21:631–635.
Wing-Kong, Ng WS, Kok CWT. Double Edge-Triggered Half-Static Clock-Gating D-Type Flip-Flop. Solid State Electronics Letters. 2021;3:1–4. Available from: https://doi.org/10.1016/j.ssel.2021.08.001
Tasnim B, Nazzal MS. A 1V 8bit 0.84µW SAR ADC for Bio-Medical applications. 13th International SoC Design Conference (ISOCC). 2016.
Guo W, Liu S, Zhu Z. An asynchronous 12-bit 50MS/s rail-to-rail Pipeline-SAR ADC in 0.18μm CMOS. Microelectronics Journal. 2016;52:23–30.
Ma R, Wang L, Li D, Ding R, Zhu Z. A 10 bit 100MS/s 5.23mW SAR ADC in 0.18um CMOS. ” Microelectronics Journal. 2018;(78) 63–72.
Zhou X, Zhang Y, Su Y. An 8-bit 35-MS/s successive approximation register ADC. 2015 IEEE International Conference on Progress in Informatics and Computing (PIC). 2015;p. 531–533. Available from: https://doi.org/10.1109/PIC.2015.7489904
Xin X, Cai JP, Chen TT, Yang QD. A 0.4-V 10-bit 10-KS/s SAR ADC in 0.18 μm CMOS for low energy wireless senor network chip. Microelectronics Journal. 2019;83:104–116. Available from: https://doi.org/10.1016/j.mejo.2018.11.017
Nasiri H, A. A 1.8V 3GS/s 7-bit time-interleaved Quasi C-2C SAR ADC using Voltage comparator time information. AEU-International journal of electronics and communication. 2017. Available from: https://doi.org/10.1016/j.aeue.2017.08.28
Gary K, Yeap. Practical Low-Power Digital VLSI Design. Kluwer Publishing. 1998.
Wakerly JF. Digital Design Principles and Practices. Prentice-Hall. 2005.

Copyright

© 2022 Sehgal & Kumar. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.

Published By Indian Society for Education and Environment (iSee)