Indian Journal of Science and Technology
Year: 2017, Volume: 10, Issue: 1, Pages: 1-10
K. Ashok Kumar* and P. Dananjayan
*Author for correspondence:
K. Ashok Kumar
Department of ECE, Pondicherry Engineering College, Puducherry - 605014, India;
Email: [email protected]
Objectives: Network on Chip (NoC) has been emerging area as communication is very complex at Chip Multi Processor and it has become more popular due to its high bandwidth and improved performance than System on Chip (SoC). Methods: This paper gives an overview of various proposals and discussed some methods for NoC and various types of topologies and types of switching techniques have given with their merits and demerits. The routing algorithms are given based on adaptively which finds the shortest distance from source to destination. Findings: This paper proposes a new architecture for low latency and low area NoC router by analyzing the different architectures for NoC by observing the number of architectures. The generic NoC has used with packet switching and deterministic routing algorithm but new techniques implemented for the routing algorithms i.e. shortest path, odd/even, north-east and south-west. Application/Improvements: NoC has improved performance that’s why it has applied in various systems, JPEG decompression, wireless transmission and security systems.
Keywords: FPGA, NoC, Routing, Switching, Topology
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