Implementation of a Novel Data Scrambling based Security Measure in Memories for VLSI Circuits

R  Vijay Sai; S  Saravanan and V  Anandkumar

doi:10.17485/ijst/2015/v8i35/86798

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Implementation of a Novel Data Scrambling based Security Measure in Memories for VLSI Circuits

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2015/v8i35/86798

Year: 2015, Volume: 8, Issue: 35, Pages: 1-6

Original Article

Implementation of a Novel Data Scrambling based Security Measure in Memories for VLSI Circuits

R. Vijay Sai ^* , S. Saravanan and V. Anandkumar

School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, India;
[email protected], [email protected], anandk[email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

This article shows the importance of security in memory for VLSI circuits based on data scrambling and overcome attacks. Security information stored in memory is very valuable. The model should not be prone to intruder attacks. The proposed method provides scrambling of information by data scrambling vectors.Instead of using some extra table for scrambling the data in cache memories, the data is divided into two halves and scrambled within to overcome extra hardware and memory requirement. This method is implemented in Verilog HDL using Model Sim which has improvement in area and memory requirement. This method is more suitable for value added applications such as smart cards and bio metric applications.
Keywords: Cache Read and Write Operations, Scrambling Vectors, Security in Memory