A Survey on Flash Translation Layer for NAND Flash Memory

Shailesh Kumar; Kumkum Dubey and P  K  Singh

doi:10.17485/ijst/2018/v11i23/125641

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A Survey on Flash Translation Layer for NAND Flash Memory

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2018/v11i23/125641

Year: 2018, Volume: 11, Issue: 23, Pages: 1-7

Original Article

A Survey on Flash Translation Layer for NAND Flash Memory

Shailesh Kumar^*, Kumkum Dubey and P. K. Singh

Computer Science and Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur - 273016, Uttar Pradesh, India; [email protected], [email protected]

^*Author for correspondence
Shailesh Kumar,
Computer Science and Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur - 273016, Uttar Pradesh, India; [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

The requirement for storage performance and capacity are increasing rapidly. NAND flash-based SSDs have been proposed as a reliable and speedy and low power consumption storage device. An important part of each SSDs is its flash translation layers (FTL). Flash translation layer is highly impact overall performance and it manages the internal data layout for storage. There are many different trade-offs involved in FTL implementation. This survey focuses on address translation technologies and provides a broad overview of existing schemes. In flash memory, flash translation layer is a very important structure and so many techniques have been proposed.

Keywords: Address Mapping, Bast, Fast, Ram Table