• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2016, Volume: 9, Issue: 29, Pages: 1-5

Original Article

A VLSI Architecture of Root Raised Cosine Filter Using Efficient Algorithm


This paper describe about a reduction of area and power using Vertical and Horizontal Common Sub-Expression Elimination Algorithm in root raised cosine filter. The common sub-expression elimination algorithm is commonly used to reduce the number of adders present the given multiplier architecture is done by reducing MPIS (Multiplications per Input Samples) and APIS (Additions per Input Samples). In the 2bit and 3-bit BCSE algorithms, shift and add method was proposed. Those provide less area than the normal multiplier. Hence algorithm is proposed to further reduce the area utilization, power consumption .Area is utilized by reducing the number of gates in the architecture. This algorithm used for implementing higher adder filters with very few adders and few stages. The proposed algorithm is used to multiply both the signed and unsigned constant multiplication. Here the adjacent co-efficient are grouped by 2bit, 4bit and 8bit grouping as per the horizontal and vertical common sub-expressions. The Shift and add method is used to reduce the number of adders. Similarly multiplexers are used for switching activity to reduce the adders and multiplication stages. These operations are applied to the RRC FIR filter with the different standards. The whole work is done in Quartus II 9.2 web edition, cyclone III. 
Keywords: 2-bit BCSE, CSE, RRC Filter, VHBCSE Algorithm 


Subscribe now for latest articles and news.