• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2018, Volume: 11, Issue: 19, Pages: 1-6

Original Article

An Efficient Architecture Implemented to Reduce the consumed Power by performing Pre Reckoning using Content Addressable Memory


Objectives: The Content Addressable Memory (CAM), are often used in various application fields to get better performance with high efficient output. The high efficient output might be obtained with minimum delay and minimum power Consumption. Methods/Statistical Analysis: The CAM is used in real time application like data search, associative computing and in the field of networking, which involves a high speed search process. A proposed banked architecture is used to control the power dissipated, which is achieved by making small variation in hardware architecture. This proposed pre reckoning -based -CAM architecture uses parameter extractor which will save the power and time. Findings: Initially parameter extractor selects the process operator, based on selected operator which will choose neighboring parameter and leaves the far away limitation. The execution of the proposed design will be done by the Xilinx software. The power consumed in every module is cumulated during execution. Application/Improvements: The obtained results also show that our choice is correct by comparing the Banking architecture with the existing one. The Proposed Banked pre reckoning architecture has minimized the average power consumption up to 30% compared with the existing one. 

Keywords: Banked Architecture, CAM, Parameter Extractor, Power Consumption, Pre- Reckoning 


Subscribe now for latest articles and news.