An Efficient Design of Sub-threshold Logic Circuits for Ultra Low Power VLSI Applications

I  A  Pindoo; M  Swain and R  Sharma

doi:10.17485/ijst/2016/v9i48/106447

Article

An Efficient Design of Sub-threshold Logic Circuits for Ultra Low Power VLSI Applications

VIEWS 667
PDF 342

Abstract
Full-Text HTML
Full-Text PDF
How to Cite

Indian Journal of Science and Technology

DOI: 10.17485/ijst/2016/v9i48/106447

Year: 2016, Volume: 9, Issue: 48, Pages: 1-5

Original Article

An Efficient Design of Sub-threshold Logic Circuits for Ultra Low Power VLSI Applications

I. A. Pindoo, M. Swain and R. Sharma

Department of Electronics and Communication, Lovely Professional University, Phagwara – 144411, Punjab, India; [email protected], [email protected], [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

In this paper, we have provided one of the solutions for achieving ultra-low power goals. The technique used is Subthreshold region operation. This technique is useful in the applications where speed is of the secondary importance, and the low power requirement is of the prime concern. We have designed an ultra-low power sub-threshold circuits in which the voltage scaling is done below the threshold voltages. The reduction in energy consumption comes at the cost of the circuit performance. We analyzed the CMOS circuits in normal as well as sub-threshold regions and the results prove that there are orders of magnitude reduction in the power consumption.

Keywords: CMOS, Subthreshold Region, Ultra Low Power VLSI