An Efficient Hardware Realization of Distributed Arithmetic Based Discrete Cosine Transform

M  Satya Rajeev  and P  Augusta Sophy Beulet

doi:10.17485/ijst/2015/v8i25/81061

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An Efficient Hardware Realization of Distributed Arithmetic Based Discrete Cosine Transform

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2015/v8i25/81061

Year: 2015, Volume: 8, Issue: 25, Pages: 1-9

Original Article

An Efficient Hardware Realization of Distributed Arithmetic Based Discrete Cosine Transform

M. Satya Rajeev^* and P. Augusta Sophy Beulet

School of Electronics Engineering, VIT University, Chennai – 600048, Tamil Nadu, India;
[email protected], [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

Objective: This paper presents an efficient design for the implementation of Discrete Cosine Transform (DCT) which is widely used in still and motion picture compression. In this work cyclic convolution and Grouped Distributed Arithmetic (GDA) technique are used. Method: In GDA, Read Only Memory (ROM) size could be reduced compared to conventional DA. For example, 1-D DCT of transform length N=13, the proposed design requires 31 Look-Up Tables (LUTs) while conventional DA requires 384 LUTs. Findings: From the synthesis results, it is found that proposed design has less area requirement and low power consumption compared to the conventional DA of same length. Conclusion: This paper proposes an efficient design for implementation of cyclic convolution based on modified GDA technique.
Keywords: Cyclic Convolution, Discrete Cosine Transform (DCT), Discrete Cosine Transform (DCT), Grouped Distributed Arithmetic (GDA), Read Only Memory (ROM)