Indian Journal of Science and Technology
Year: 2015, Volume: 8, Issue: 25, Pages: 1-9
Budda Nagendra Reddy* and P. Augusta Sophy Beulet
Background: Floating Point(FP) computation is an indispensible task in various applications. The floating point additions and multiplications are core operations in complex multiplication, in which inputs should be given in IEEE 754 standard formats. Methods: The proposed design performs one double precision, or two single precision addition and multiplication operations in parallel, have been designed efficiently using resource sharing for both precision operands with minimal multiplexing circuitry. The proposed floating point multiplier makes use of Vedic multiplication algorithm, because in array multiplication sharing of multiplication is not possible. Findings: The proposed architecture has been synthesized using 0.18µm standard cell library. Compared to previous architectures the proposed DPdSP architecture has 20% reduced power and 5% area reduction. Conclusion: The DPdSP adder and multiplier consume less power than the conventional adder. Using Vedic multiplication technique shows a minimum power compared with all other type of architecture.
Keywords: Double Precision, Floating Point Arithmetic, Single Precision, Urdhva Tiryakbhyam, Vedic Mathematics
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