Indian Journal of Science and Technology
DOI: 10.17485/ijst/2015/v8i7/63604
Year: 2015, Volume: 8, Issue: 7, Pages: 664–669
Original Article
L. S. Usharani 1* , P. Thiruvalar Selvan2 and G. Jagajothi 1
1 Periyar Maniammai University, Vallam, Thanjavur, India; usha_32@yahoo.com
2 TRP Engineering College (SRM Groups), Tiruchirappalli, India; thiruvalar@gmail.com.
Objective: This research focuses on design and implementation of FPGA hardware architecture based image de-noising algorithm with automatic detection and correction of impulse noise. With the proposed hardware, image or video camera can be interfaced with the implementing hardware for de-noising of salt and pepper noise called impulse noise.
Methods/Analysis: The algorithms proposed in this research mainly work on images to identify the impulse noise affected pixel and correct only the corrupted pixel instead of uncorrupted. Also the novelty method modifies the existed features of various de-noising techniques using real time, low power FPGA architecture for the noise detection and correction.
Findings: The proposed research is in two stages namely modified boundary discriminative noise detection and recursive median filter based correction technique. These two stages are tested for various noise densities and delivered better de-noising factor than the existing algorithms. The simulation results of the implemented algorithm prove efficiency of 98% noise reduction factor for 90% corrupted image or video.
Keywords: BDND, FGPA, Impulse Noise, Median Filters, MSE, Non Linear Filters
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