Indian Journal of Science and Technology
DOI: 10.17485/ijst/2013/v6i4.17
Year: 2013, Volume: 6, Issue: 4, Pages: 1-7
Original Article
Bharathi N.1 * and P. Neelamegam2
1 School of Computing, SASTRA University, [email protected]
2 School of Electrical & Electronics Engineering, SASTRA University, [email protected]
*Author For Correspondence
Bharathi N
School of Computing, SASTRA University,
Email: [email protected]
The emerging reconfigurable computing reduces the need of computation exhaustive applications, which are always demanding more efficient computation hardware. The partially reconfigurable Field Programmable Gate Arrays (FPGA) are highly suitable for performance improvement. This paper discusses the study of FPGA utilization when scheduling fixed size configurable computation hardware block (CCHB) by applying a heuristic. Based on the parameters (speedup, CCHB size etc.,) associated with the independent CCHBs, scheduling is performed and it is repeated for various sizes of FPGA. From the study of four applications from benchmark suite, it is observed that the device utilization is increased with size of CCHBs not greater than 0.5 times or not less than 0.85 times of the size of FPGA.
Keywords: Field Programmable Gate Array (FPGA), Scheduling, Configurable Computation Hardware Block (CCHB), Response Time, Utilization.
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