Indian Journal of Science and Technology

Abstract

Testing and planning of very large scale integration circuits are the most challenging aspects now days, whenever a chip manufacture takes place many important parameters like doping of substrate, channel length of gate oxide and the thickness of the oxide vary during the fabrication of VLSI circuits that has an adverse impact on the circuit performance. In this paper, we demonstrate nearer examination of process variation on single bit domino full adder with single bit static full adder. This paper shows the variation of threshold voltage, oxide thickness and channel length on the execution parameter of single bit full adder that is designed by using a different transistor count like 10T, 28T, 22T. The result demonstrates that when 8.33% variation takes place in channel length than 2.078% increment in the power and 0.132% decrement in delay and 1.75% increase in power delay product of 22T domino full adder circuit, that is a minimum variation when compared with other single bit static full adders 10T and 28T. In threshold voltage when 1.6% variation occurs, then 0.76% decrement in power and 0.76% decrement in power delay product of 22 transistor domino full adder circuit, that is a minimum variation when compared with other single bit static full adder 10T and 28T. In oxide thickness 14.28% variation takes place, then 0.76% reduction in power and 2.49% decrement in PDP of 22T domino full adder circuit that is a minimum variation when compared with other single bit static full adder 28T and 10T. All simulations are done by using the tanner tool with 90nm PTM technology node with 1.1 volt supply voltage.
Keywords: Complementary Metal Oxide Semiconductor (CMOS), Metal Oxide Semiconductor (MOS), N-type Metal Oxide Semiconductor (NMOS), Power Delay Product (PDP), P-type Metal Oxide Semiconductor (PMOS), Threshold Voltage (VT), Very Large Scale Integration (VLSI)