Comparison of Hardware Design Complexity to Extract Depth Map from Stereo Images

Ji Yong; Lee; Young Hyung; Kim  and Yong Hwan; Lee

doi:10.17485/ijst/2015/v8iS8/70529

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Comparison of Hardware Design Complexity to Extract Depth Map from Stereo Images

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Indian Journal of Science and Technology

DOI: 10.17485/ijst/2015/v8iS8/70529

Year: 2015, Volume: 8, Issue: Supplementary 8, Pages: 1-8

Original Article

Comparison of Hardware Design Complexity to Extract Depth Map from Stereo Images

Ji-Yong, Lee¹ , Young-Hyung, Kim² and Yong-Hwan, Lee^3*

¹Department of Electronics Engineering, Kumoh National Institute of Technology, Gumi, 730-701, South Korea
² Department of IT Convergence, Kumoh National Institute of Technology, Gumi, 730-701, South Korea
³School of Electronics Engineering, Kumoh National Institute of Technology, Gumi, 730-701, South Korea; [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.

Abstract

Computer vision technology has been researched in the field of mobile robots, intelligent vehicle navigation aids, obstacle avoidance and many others. We implement fast and accurate census transform algorithm in software and hardware for computer vision to extract depth map from different two images. We have designed in C language and Verilog hardware description language, verified by Modelsim, and implemented on FPGA for real-time processing capability. We have converted the census transform algorithm to hardware structure to compute depth map for two images in parallel processing. The resultant system extracts the depth information within search-range of 30 from 240 x 320 image using the window size of 3by3, 5by5 and 7by7, respectively.
Keywords: Depth Map, Image Matching, Stereo Vision