Indian Journal of Science and Technology
DOI: 10.17485/ijst/2016/v9i47/104400
Year: 2016, Volume: 9, Issue: 47, Pages: 1-4
Original Article
S. Nazeer Hussain* and K. Hari Kishore
KL University, Green Fields, Vaddeswaram, Vijayawada, Guntur - 522502, Andhra Pradesh, India; [email protected], [email protected]
*Author for correspondence
S. Nazeer Hussain
KL University, Green Fields, Vaddeswaram, Vijayawada, Guntur - 522502, Andhra Pradesh, India; [email protected]
In the VLSI chip designing process, Floor-planning is one of the vital stages which in turn have Placement and Routing tasks. This paper concentrates on solving the problems which occur in VLSI floor planning and gives an overview of placement and routing problems in ICs. This approach depends on recursive optimization prototypes with redefined algorithm. The searching for best solutions is carried out by Genetic Algorithm (GA) on each iteration since these algorithms is already known and proven to solve similar type of problems. GA has been tested randomly and is simulated. By conducting experiments on GA we can realize optimized solutions for the above said problems.
Keywords: Field Programmable Gate Arrays (FPGA) Placement, Genetic Algorithm (GA), VLSI Design
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