Indian Journal of Science and Technology
Year: 2016, Volume: 9, Issue: 37, Pages: 1-4
R.Dhanabal* andSarat Kumar Sahoo
Department of Micro and Nano Electronics, VIT University, Vellore - 632014, Tamil Nadu, India; [email protected]
*Author for correspondence
Department of Micro and Nano Electronics
Email: [email protected]
Objectives: To design a 32-bit IEEE 754 floating point standard based MAC unit using 15 nm FinFET. In MAC unit given data is multiplied and accumulated in a register which are processed separately as exponent and mantissa but there are some issues regarding area power and timing, compromising these constraints is bit difficult. Methods: The proposed architecture of floating point MAC unit is majorly divided into multiplier and accumulator components in these blocks the sub blocks are designed with Han-Carlson adder, Vedic multiplier, barrel shifter and comparator. Findings: The previous work was done in Hardware Description Language (HDL) in which the design will map to CMOS or pass transistor components after synthesis so designing of each component with transistors of 15 nm FINFET becomes vital. The entire design is carried out in cadence virtuoso and layout editor for timing, area and power. The performance can be increased if the computations are performed with less number of transistors. However, the decimal operations have been limited due to the increase in cost and complexity of hardware components. DFP arithmetic is used for the complex computations, it consumes more power because of the area it occupied when implemented in hardware. Improvements/Applications: Because of battery driven property low power with high performance are given major importance.
Keywords: Barrel Shifter and Comparator, Han-Carlson Adder, Leading One Detector, MAC Unit (Multiplication and Accumulation Unit), Vedic Multiplier
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