Indian Journal of Science and Technology
Year: 2015, Volume: 8, Issue: 35, Pages: 1-8
S. Manjula* and D. Selvathi
Mepco Schlenk Engineering College, Sivakasi - 626005, Tamil Nadu, India; [email protected]
In this paper, an Inductively Degenerated Cascode Low Noise Amplifier (IDCLNA) is designed using TSMC 0.13 μm RF CMOS technology. For improving the performances of LNA, modifications are done in conventional IDCLNA. They are 1. Forward Body Bias (FBB) technique is applied to reduce the supply voltage. 2. The inductor is added between main and cascode transistors for increasing the gain. 3. To reduce the noise factor of cascode stage, an inductor is inserted at the gate of cascode stage. 4. For improving the stability factor, the modified resistive and capacitive shunt feedback is used. The proposed LNA produces 10.7 dB voltage gain, 3.27 dB noise figure, -9.1 dBm IIP3 and 957 μW power consumption. For optimizing the design parameters of proposed LNA, the popular optimization technique like Particle Swarm Optimization (PSO) algorithm is used to improve the performance measures. The optimized LNA achieves 12.6 dB voltage gain, 3.19 dB noise figure and consumes 869 μW power. The optimized results produce the good Figure of Merit (FOM) of 6.6.
Keywords: Figure of Merit, LNA, Power Consumption and PSO
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