Indian Journal of Science and Technology
Year: 2019, Volume: 12, Issue: 36, Pages: 1-7
Disha Gaude*, Bathini Poornima, K.M. Sudharshan and Prashant V. Joshi
*Author for correspondence
Department of ECE, REVA University, Yelahanka, Bengaluru − 560064, Karnataka, India; [email protected]
Objective: To design 4-bit flash Analog to Digital Converter (ADC) for high speed applications. The objectives of the project are to design sample and hold circuit, high efficient DAC circuit, to design a high speed, low power and minimum delay CMOS comparator and thermometer to binary code convertor logic. Methodology: The main block of flash ADC is designing of comparator. For high speed applications Flash ADC requires comparator having high sensitivity and low power dissipation. In this we have used CMOS comparator with cascaded stages, each stage will help in increasing gain and sensitivity and reducing the all types of noises. First stage is the pre-amplifier stage whose output is given to the input of decision stage. Decision stage is followed by post-amplifier stage. Findings: In most papers for designing flash ADC they used dynamic comparator, these dynamic comparators are more difficult to design and will give more power dissipation. In our design we used CMOS comparator with cascaded stages, this type of comparator provides less power dissipation, less delay and high sensitivity by reducing the noise like kickback noise, offset voltages etc. The design is simulated in 180 nm Technology with Cadence Virtuoso Tool and LT spice. Designed comparator has Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) error considered for design within +/- 0.5LSB. For N-bit flash ADC we have 2N-1 comparators, whose outputs will generate patterns of 0’s and 1’s in form of thermometer code; in order to convert it into binary format we have used mux encoder. This mux encoder logic reduces area and very easy to design compared to other methods. Applications/ Improvements: Flash ADC’s are used in various applications ranging from radar receivers, digital sampling, and LAN interface. The proposed design achieved a power dissipation of 0.121 mW with delay of 19.4 ns. The comparator block is designed and simulated. The sensitivity of the comparator is 0.003V.
Keywords: CMOS Comparator, DNL and Binary Code Converter, Flash Analog to Digital Converter (ADC), Integral NonLinearity (INL)
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