Indian Journal of Science and Technology
DOI: 10.17485/ijst/2016/v9i45/103389
Year: 2016, Volume: 9, Issue: 45, Pages: 1-4
Original Article
D. Jayakumar1* and E. Logashanmugam2
1Department of ECE, St. Peter’s University Chennai - 600054 , Tamil Nadu, India; [email protected] 2Department of ECE, Sathyabama University, Chennai - 600119, Tamil Nadu, India; [email protected]
*Author for correspondence
D. Jayakumar Department of ECE, St. Peter’s University Chennai - 600054 , Tamil Nadu, India; [email protected]
Objectives: FFT algorithm is used for enhancing the performance of DFT.In the previous years, various types of FFT algorithms have been introduced. Particularly, the pipeline algorithms have been reputed as proper algorithms for processing high-speed data. Some pipeline FFT algorithms like split radix, radix-2 and the mixed radix have been developed. Methods: In the existing method of Radix-2 SDF FFT has more hardware utilization and also computational stages are increased. Findings: To conquer this problem, we developed a combined radix-2, 4 & 8 butterfly elements based Single path Delay Feedback (SDF) fast fourier transform method for reducing the computational stages in this paper. The developed method has the identical number of multipliers and the smaller number of stages and butterfly elements than the existing radix-2 FFT. Improvements: This architecture offers 62.47% reduction in LUTs, 58.78% reduction in slices, and 37.85% reduction in delay and 30.86% reduction in power consumption than the existing method.
Keywords: Discrete Fourier Transform (DFT), Fast Fourier Transform (FFT), Look Up Tables (LUTs), Single path Delay Feedback (SDF),
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