• P-ISSN 0974-6846 E-ISSN 0974-5645

Indian Journal of Science and Technology


Indian Journal of Science and Technology

Year: 2015, Volume: 8, Issue: Supplementary 2, Pages: 1-7

Original Article

Design of Low Power and Area Efficient 4-bit Arithmetic and Logic Unit using Nanoscale FinFET


In order to strive in VLSI Technology, we have to keep up with the Moore’s law which states that in every 18 month number of transistors gets doubled on a chip. But as we scale down the transistor size problems like Short Channel Effects (SCE), Sub-threshold voltage variation, Drain Induced Barrier Lowering (DIBL), Gate oxide tunnelling leakage etc., comes into the account. To overcome the above problems we moved towards the FinFET based transistor. In this paper we have proposed the “Design of Low power 4-bit arithmetic & logic unit using nanoscale FinFET”. Arithmetic Logic Unit (ALU) is the backbone of any processor, we have performed the logical operations like AND, OR, Inverter, 2’s complement of the number etc. & Arithmetic operation like addition, subtraction, multiplication, parity generation etc. Different techniques are used to achieve the low power on different modules in the design.
Keywords: Adder, ALU, FinFET, SCE, Transmission Gate


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