Indian Journal of Science and Technology
DOI: 10.17485/ijst/2016/v9i44/99518
Year: 2016, Volume: 9, Issue: 44, Pages: 1-5
Original Article
Vikash Kumar*, Prashant Gupta, Shashank Kumar Ranu, Manish Kumar Pandey, Aminul Islam
Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University), Mesra, Ranchi – 835215, Jharkhand, India; [email protected], [email protected],[email protected], [email protected], [email protected]
*Author for correspondence
Vikash Kumar
Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University), Mesra, Ranchi – 835215, Jharkhand, India; [email protected]
Objective: The objective of this paper is to realize an n-bit reversible number generator. Several designs of number generator and their corresponding constraints with feedback controller and initial state have also been discussed. Method/Analysis: The proposed design is validated by simulating the results in Verilog HDL. Findings: In this paper a design is presented to implement an n bit number generator as a finite state automation, using reversible logic for the implementation of the transition network. A realizable circuit is designed to implement the n-bit number generator using feedback controllers. Novelty/Improvement: With the use of reversible logic, the designed circuit reaches all the possible states and consumes no power.
Keywords: Finite State Automation, Number Generator, Reversible Computing, Reversible Logic Synthesis
Subscribe now for latest articles and news.
